1. Field of the Invention
This invention relates generally to data recovery. More particularly, it relates to a calibration technique for minimizing mismatch between oscillators in a burst mode data recovery circuit.
2. Background of Related Art
In creating a burst mode data recovery circuit, it is desirable to use multiple voltage controlled oscillators (VCOs) to reduce phase and frequency deviations in the recovered time base signal. These VCOs must (1) oscillate at a specific frequency within a tolerance band; and (2) must match output frequency with each other to within this tolerance band. The degree of error allowed within this tolerance band limits the length that the received information packet may be detected without introducing bit errors.
A basic technique for burst mode data recovery was pioneered by Alfred Dunlop, et al. at what is now LUCENT TECHNOLOGIES in 1992, as disclosed in U.S. Pat. No. 5,237,290, as exemplified herein in FIG. 2.
As shown in FIG. 2, Dunlop discloses a clock recovery circuit 10 that uses indirect tuning of variable frequency voltage controlled oscillators (VCOs) 11, 12. To indirectly tune the VCOs 11, 12, Dunlop uses a phase locked loop (PLL) clock recovery circuit 20 that relies on closely replicated physical and electrical characteristics of the multiple oscillators 11, 12, 18. However, since Dunlop's circuits are only indirectly tuned, the circuit's oscillators 11, 12, 18 will inherently run at somewhat different frequencies, based on a tolerance. That frequency difference between oscillators will be emphasized, causing frequency drift and possible loss of alignment between the recovered clock signal and incoming data when the input signal is not transitioning, as it is during unbroken strings of ones and zeros or consecutive identical digits (CIDs). When transitions are absent from the input signal for a prolonged period and the recovered clock drifts, the recovered clock will be out of phase when the transitions reappear, thereby causing errors until the oscillators can be resynchronized.
Thus, the indirect tuning taught by Dunlop's burst mode optical receiver is seen by the present inventors as suffering from VCO mismatch. While Dunlop's circuit requires manual component selection to provide as best a good frequency match within a given tolerance, Dunlop teaches accommodation of a significant tolerance nonetheless. Dunlop fails to recognize a need for, attempt or disclose direct calibration or tuning of the VCOs 11, 12.
Frequency calibration was attempted by W. Pitio, et al. in this regard in 1992, as disclosed in U.S. Pat. No. 5,843,980, and as shown herein in FIG. 3.
In particular, as shown in FIG. 3, Pitio teaches the use of a number of VCOs 31, 32 that are calibrated using a Phase Locked Loop (PLL) and sample-hold 41, 42 to set the frequency of the respective VCOs 31, 32 during a calibration routine, and to hold the calibrated VCO control parameters while the VCOs 31, 32 are in use. While Pitio provides a valid approach, the present inventors deem such an approach limiting to today's IC integration demands. For instance, phase locked loops (PLLs) are generally analog circuits and can be difficult to integrate with VLSI digital circuits. The need to minimize the use of large passive components, found in analog PLL loop filters, is of particular concern.
There is a need for a technique for matching or calibrating multiple VCOs in such tight tolerance with one another so as to allow lower bit error rates (BER) and/or to allow data packets containing longer CIDs to pass.